例1:试用两片74LS148设计一个16-4线优先编码器。允许附加必要的门电路。
解:根据优先编码器的逻辑功能,列出16-4线优先编码器的逻辑功能表如表1。 ~ 为编码输入端,其中 的优先级最高, 的优先级最低。 ~ 为编码输出端。输入输出均为低电平有效。
表1 16-4线优先编码器逻辑功能表
输入 |
输出 |
A0 |
A1 |
A2 |
A3 |
A4 |
A5 |
A6 |
A7 |
A8 |
A9 |
A10 |
A11 |
A12 |
A13 |
A14 |
A15 |
Z3 |
Z2 |
Z1 |
Z0 |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
0 |
0 |
0 |
0 |
0 |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
0 |
1 |
0 |
0 |
0 |
1 |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
0 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
× |
× |
× |
× |
× |
× |
× |
× |
× |
× |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
× |
× |
× |
× |
× |
× |
× |
× |
× |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
× |
× |
× |
× |
× |
× |
× |
× |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
× |
× |
× |
× |
× |
× |
× |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
× |
× |
× |
× |
× |
× |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
× |
× |
× |
× |
× |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
× |
× |
× |
× |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
× |
× |
× |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
× |
× |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
× |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
从表1中还可以看出,用多个优先编码器扩展成其他多输入的优先编码器时,根据优先编码器的特点,组成的扩展电路中,始终只有一个编码器工作。优先级高的输入所在的编码器(所在的优先编码器为编码器Ⅰ,用74LS148(Ⅰ)表示)接在前面,优先级低的输入所在的编码器(所在的优先编码器为编码器Ⅱ,用72LS148(Ⅱ)表示)接在后面。且编码器按连接顺序依次开始工作(即74LS148(Ⅰ)先工作,72LS148(Ⅱ)后工作),当后面的编码器工作时,前面的编码器处于工作但没输入的状态。最前面的编码器始终处于工作状态(将输入端接地)。
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